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混合信號兼顧多層次模擬軟件 Dolphin Integration SoC GDS v6.7.1 英文版 CD

混合信號兼顧多層次模擬軟件,能完全符合混合模擬與邏輯訊號電路的需求。混合訊號指的是SMASH能處理模擬或是連續時間的訊號與不連續時間的訊號,例如:邏輯(二進制binary)或數字(十進制decimal)。多層次指的是SMASH並沒有被限制在某些modeling level上,即SMASH能處理晶體管層次、閘階層次、功能層次、行為層次並與來自於模擬與邏輯的子電路加以混合模擬。意味著SMASH可用在任何層次上的設計作一些精確的電路修正,這表示你將能輕易處理任何復雜性的電路。另外SMASH有強大的多語言功能,能與SPICE、Verilog-HDL、 VHDL、ABCD(C-language)與VHDL-AMS兼容,可以將模擬區塊以SPICE語法描述與數字區塊以Verilog-HDL語法或VHDL語法描述的設計作多層次混合信號模擬。 SMASH能快速地模擬驗證所設計的混合信號芯片,非常適合用來解決混合信號芯片設計問題,以提供高效能的混合信號芯片設計模擬驗證環境,減化複雜電路模擬驗證的程序,縮短芯片設計的時程。
SoC GDS Vision
Analyze, Convert Verify
Standard Layout Databases


SoC GDS offers an intuitive user interface, providing advanced productivity enhancing functionalities, throughout the design creation and validation chains.
SoC GDS addresses a wide range of needs, from quick and easy layout viewing, to final insertions of cells before mask generation, via advanced hierarchical integration of blocks, including solutions for preserving confidentiality in case of verifications.
This framework independent Streamer focuses on standard exchange formats for bridging proprietary EDA Frameworks.
Through dedicated options, SoC GDS fits the needs of Virtual Component providers, SoC integrators and process/product engineers. It is also the ideal solution to complete quality procedures for acceptance of layout databases by chip finishing teams, mask shops or silicon foundries.
Key Features
Integrated hierarchy browser
OpenAccess, GDSII and LEF
Ultra-fast layout loading and display
Multi-platform GUI and CLI
Interoperable with frameworks
Graphical and geometrical comparison
Virtual Socket Builder for generation of black boxes enabling verification and integration
Virtual Cut for layout extraction
Batch processing mode for automated verification and integration
Options for a wide range of applications
SoC GDS Analyzer is the entry-level option providing optimized display capabilities including color and pattern configuration file compatibility with Cadence for drop-in replacement or complementing in design flows.
SoC GDS Babelizer extends the speed and power of SoC GDS Analyzer with advanced hierarchical navigation, input format support complemented with OpenAccess and LEF, as well as (VC)LEF generation. Verification of layouts is accelerated through hierarchical graphic comparison of cells and hierarchical display of annotated nets.
SoC GDS Binder enables socket creation and verification for system-level integration of blocks and ViCs (Virtual Components). Delivery of layouts is accelerated by creation of LVS sockets (black box), hierarchical geometrical comparison of cells and a powerful interpreted scripting language for repetitive processing. An innovative feature for Virtual Cut allows to extract just a part of a layout for verification while totally preserving confidentiality of the rest of the SoC.

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